Optimum buffer size for dynamic voltage processors


Manzak A., Chakrabarti C.

INTEGRATED CIRCUIT AND SYSTEM DESIGN, vol.3254, pp.711-721, 2004 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 3254
  • Publication Date: 2004
  • Title of Journal : INTEGRATED CIRCUIT AND SYSTEM DESIGN
  • Page Numbers: pp.711-721

Abstract

This paper addresses the problem of calculating optimum buffer size for a dynamic voltage scaling processor. We determine the minimum required buffer size giving minimum energy solution for periodic (single, multiple) or aperiodic tasks. The calculations are based on information about data size (maximum, minimum), execution time (best case, worst case), and deadlines.